The JTAG port from the PXA270 processor is brought out to small test pads on the Zipit2’s board (thanks to prpplague for finding it). These pads are unmarked and are soldermasked over on the old style board that has the corrections. But, they are not soldermasked over on the newer style board and are assumed to be in the same location. The picture to the right shows the locations of the pads.
GPSFan has been testing out the JTAG port using a
Flyswatter.
His JTAG setup is shown to the right and he has written a tutorial below:
- Wire up all the JTAG signals
- nSRST needs to be connected to the reset button
- Four 91k pullups are connected to vTarget
- vTarget is connected to the gold pad near the power chip pin10 (See picture)
- Get the latest OpenOCD sources (tested with svn 838)
- Get the latest FDTI
libfdti2xx (tested with libftdi2xx0.4.13) - Put WinTypes.h and ftd2xx.h into the /openocd/src/jtag directory
- Run ./bootsrtap from /openocd
- Run ./configire –enable-ft2232-ftd2xx
- Run make
- Copy the resulting openocd executable from /openocd/src somewhere handy say /xyz/
- Copy /openocd/src/target/xscale/debug_handler.bin to /xyz/xscale/
- Checkout the misc module from cvs (More Info)
- Use the z2.cfg found in the misc module
- Make sure you have usbfs mounted on /proc/bus/usb
- Connect the flyswatter to the PC’s USB port
- Connect the z2 to the Flyswatter
- Plug in the z2’s wall adapter to power and to the z2
- Do not push the z2’s power button
- As root in /xyz, run ./openocd -f z2.cfg
- As a normal user run telnet localhost 3333
- You should get the openocd prompt
- At the prompt run the command “reset halt”
- You should then be able to probe the flash, step, read and write flash memory
- To be able to use SDRAM, you must set up the PXA270’s config registers,
the subject of a future update.